memo Project Status (03/17/2017 - 17:18:03) | |||
Project File: | memo.ise | Implementation State: | Programming File Generated |
Module Name: | MOD_memo |
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No Errors |
Target Device: | xc6slx9-3tqg144 |
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37 Warnings |
Product Version: | ISE 11.5 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 193 |