memo Project Status (03/17/2017 - 17:18:03)
Project File: memo.ise Implementation State: Programming File Generated
Module Name: MOD_memo
  • Errors:
No Errors
Target Device: xc6slx9-3tqg144
  • Warnings:
37 Warnings
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
 [[c`jHIk@HED`N@Jjhc[[[[[<[FjDOIN;[[=[FjDOIN;B}[h/}[\? \\c`jHIk@HED`N@Jjhc\\\\<\FjDOIN:}\h/}\^^AC>^^<^=u__O@AC? __AC>c____<_FjDOIN:}_h/}_>p``O@AC?@eKeᆳne8ne2:8eyzKᆳn0n2:0~wv~ =: =v{eye =eze:e =gggz}gapggy{pgggy{8g ${mKmᆳnm*nm*snACmfAMHfAMHKᆳn"n"fAMHfAMHJIODEhJIODEhmmJIODEhmJIODEhn nnJIODEhcnnnnnFjDOIN:}nh/}nppppppACpppACppqqACvKvᆳnv*nv*swACvfAMHfAMHKᆳn"n"fAMHfAMHc`jHIk@HED`N@Jjhc`jHIk@HED`N@Jjhvvc`jHIk@HED`N@Jjhvc`jHIk@HED`N@Jjhw wwc`jHIk@HED`N@JjhcwwwwwFjDOIN:}wh/}wyyyyyyACyyyACypzzACKᆳn*n*sACOEMHOEMHKᆳn"n"OEMHOEMHJIODEhJIODEhJIODEhJIODEh JIODEhcFjDOIN:}h/} ACACpACKᆳn*n*sACOEMHOEMHKᆳn"n"OEMHOEMH c`jHIk@HED`N@Jjhc`jHIk@HED`N@Jjh c`jHIk@HED`N@Jjhc`jHIk@HED`N@Jjh c`jHIk@HED`N@JjhcFjDOIN:}h/} zACIGN=RIGHT>128
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 193 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Average Fanout of Non-Clock Nets 3.96      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 17. Mrz 17:13:48 2017036 Warnings10 Infos
Translation ReportCurrentFr 17. Mrz 17:14:23 201701 Warning0
Map ReportCurrentFr 17. Mrz 17:14:50 2017006 Infos
Place and Route ReportCurrentFr 17. Mrz 17:15:58 2017005 Infos
Power Report     
Post-PAR Static Timing ReportCurrentFr 17. Mrz 17:16:10 2017003 Infos
Bitgen ReportCurrentFr 17. Mrz 17:18:03 2017000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 03/17/2017 - 17:18:03